1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to protection of integrated circuits from electrostatic discharge.
2. Description of Related Art
Electrostatic discharge (ESD) is a known cause of failure of integrated circuit devices. Large electrostatically generated voltages can result from human handling of chip-level and even board-level circuits. Reliability of such circuits can be improved by including ESD protectors as part of the circuit design.
ESD frequently is presented on a power supply terminal such as a voltage supply line of a circuit. Although ESD voltages may be quite large, they tend to be characterized by very short rise- and fall-times so that an ESD protector may not be able to respond directly to a “zap” from an ESD source. Accordingly, an RC delay circuit may be connected to the voltage supply line of a device in order to provide the ESD protector time to respond to an ESD event, typically by momentarily shunting the drain supply line to ground.
Fabrication of a resistor in an integrated circuit forces an inefficient trade-off between resistor value and use of chip area, large resistance being required to achieve large delay, and large chip area being required to implement large resistance. Accordingly, some prior-art attempts to create a delay circuit for an ESD protector have substituted a transistor for a resistor in an RC circuit. However, the effective resistance of a transistor may be rather small, so that it is difficult to create a large delay following this approach.
A need thus exists in the prior art for a simple and effective RC circuit implementation for an ESD protector which is both efficient in its use of chip area and is capable of providing a significant RC delay.